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80c652/83c652 cmos single-chip 8-bit microcontrollers product specification 1996 aug 15 integrated circuits ic20 data handbook
port 0 port 1 port 2 port 3 address and data bus address bus v ss v dd alternate functions rst xtal1 xtal2 ale psen rxd txd int0 int1 t0 t1 wr rd scl sda ea phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 2 1996 aug 15 description the p80c652/83c652 single-chip 8-bit microcontroller is manufactured in an advanced cmos process and is a derivative of the 80c51 microcontroller family . the 80c652/83c652 has the same instruction set as the 80c51. three versions of the derivative exist: 83c652 e 8k bytes mask programmable rom 80c652 e romless version 87c652 e eprom version (described in a separate chapter) this device provides architectural enhancements that make it applicable in a variety of applications for general control systems. the 8xc652 contains a non-volatile 8k 8 read-only program memory, a volatile 256 8 read/write data memory, four 8-bit i/o ports, two 16-bit timer/event counters (identical to the timers of the 80c51), a multi-source, two-priority-level, nested interrupt structure, an i 2 c interface, uart and on-chip oscillator and timing circuits. for systems that require extra capability, the 8xc652 can be expanded using standard ttl compatible memories and logic. the device also functions as an arithmetic processor having facilities for both binary and bcd arithmetic plus bit-handling capabilities. the instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and 17 three-byte. with a 16(24)mhz crystal, 58% of the instructions are executed in 0.75(0.5) m s and 40% in 1.5(1) m s. multiply and divide instructions require 3(2) m s. logic symbol features ? 80c51 central processing unit ? 8k 8 rom expandable externally to 64k bytes ? 256 8 ram, expandable externally to 64k bytes ? two standard 16-bit timer/counters ? four 8-bit i/o ports ? i 2 c-bus serial i/o port with byte oriented master and slave functions ? full-duplex uart facilities ? power control modes idle mode power-down mode ? rom code protection ? extended frequency range: 1.2 to 24 mhz ? three operating ambient temperature ranges: 0 to +70 c 40 to +85 c 40 to +125 c pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 scl/p1.6 rst rxd/p3.0 txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 sda/p1.7 rd /p3.7 xtal2 xtal1 v ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p2.5/a13 p2.6/a14 p2.7/a15 psen ale ea p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v dd 6 1 40 7 17 39 29 18 28 44 34 1 11 33 23 12 22 wr /p3.6 plastic dual in-line package plastic leaded chip carrier plastic quad flat pack
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 3 ceramic and plastic leaded chip carrier pin functions 6 1 40 7 17 39 29 18 28 ceramic and plastic leaded chip carrier pin function pin function 1 nc* 23 nc* 2 p1.0 24 p2.0/a8 3 p1.1 25 p2.1/a9 4 p1.2 26 p2.2/a10 5 p1.3 27 p2.3/a11 6 p1.4 28 p2.4/a12 7 p1.5 29 p2.5/a13 8 p1.6/scl 30 p2.6/a14 9 p1.7/sda 31 p2.7/a15 10 rst 32 psen 11 p3.0/rxd 33 ale 12 nc* 34 nc* 13 p3.1/txd 35 ea 14 p3.2/int0 36 p0.7/ad7 15 p3.3/int1 37 p0.6/ad6 16 p3.4/t0 38 p0.5/ad5 17 p3.5/t1 39 p0.4/ad4 18 p3.6/wr 40 p0.3/ad3 19 p3.7/rd 41 p0.2/ad2 20 xtal2 42 p0.1/ad1 21 xtal1 43 p0.0/ad0 22 v ss 44 v dd *do not connect plastic quad flat pack pin functions 44 34 1 11 33 23 12 22 plastic quad flat pack pin function pin function 1 p1.5 23 p2.5/a13 2 p1.6/scl 24 p2.6/a14 3 p1.7/sda 25 p2.7/a15 4 rst 26 psen 5 p3.0/rxd 27 ale 6 v ss4 28 v ss2 7 p3.1/txd 29 ea /v pp 8 p3.2/int0 30 p0.7/ad7 9 p3.3/int1 31 p0.6/ad6 10 p3.4/t0 32 p0.5/ad5 11 p3.5/t1 33 p0.4/ad4 12 p3.6/wr 34 p0.3/ad3 13 p3.7/rd 35 p0.2/ad2 14 xtal2 36 p0.1/ad1 15 xtal1 37 p0.0/ad0 16 v ss1 38 v dd 17 nc* 39 v ss3 18 p2.0/a8 40 p1.0 19 p2.1/a9 41 p1.1 20 p2.2/a10 42 p1.2 21 p2.3/a11 43 p1.3 22 p2.4/a12 44 p1.4 *do not connect notes to qfp only: 1. due to emc improvements, all v ss pins (6, 16, 28, 39) must be connected to v ss on the 80c652/83c652.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 4 order information philips part order number part marking philips north america part order number temperature range ( c) freq romless rom 3 drawing number romless rom and package mhz 1,2 p80c652fbp p83c652fbp/xxx sot129-1 p80c652fbpn p83c652fbpn 0 to +70, plastic dual in-line package 16 p80c652fba p83c652fba/xxx sot187-2 p80c652fbaa p83c652fbaa 0 to +70, plastic leaded chip carrier 16 p80c652fbb p83c652fbb/xxx sot307-2 4 p80c652fbbb p83c652fbbb 0 to +70, plastic quad flat pack 16 p80c652ffp p83c652ffp/xxx sot129-1 p80c652ffpn p83c652ffpn 40 to +85, plastic dual in-line package 16 p80c652ffa p83c652ffa/xxx sot187-2 p80c652ffaa p83c652ffaa 40 to +85, plastic leaded chip carrier 16 p80c652ffb p83c652ffb/xxx sot307-2 4 p80c652ffbb p83c652ffbb 40 to +85, plastic quad flat pack 16 p80c652fhp p83c652fhp/xxx sot129-1 p80c652fhpn p83c652fhpn 40 to +125, plastic dual in-line package 16 p80c652fha p83c652fha/xxx sot187-2 p80c652fhaa p83c652fhaa 40 to +125, plastic leaded chip carrier 16 p80c652fhb p83c652fhb/xxx sot307-2 4 p80c652fhbb p83c652fhbb 40 to +125, plastic quad flat pack 16 p80c652ibp p83c652ibp/xxx sot129-1 p80c652ibpn p83c652ibpn 0 to +70, plastic dual in-line package 24 p80c652iba p83c652iba/xxx sot187-2 p80c652ibaa p83c652ibaa 0 to +70, plastic leaded chip carrier 24 p80c652ibb p83c652ibb/xxx sot307-2 4 p80c652ibbb p83c652ibbb 0 to +70, plastic quad flat pack 24 p80c652ifp p83c652ifp/xxx sot129-1 p80c652ifpn p83c652ifpn 40 to +85, plastic dual in-line package 24 p80c652ifa p83c652ifa/xxx sot187-2 p80c652ifaa p83c652ifaa 40 to +85, plastic leaded chip carrier 24 p80c652ifb p83c652ifb/xxx sot307-2 4 p80c652ifbb p83c652ifbb 40 to +85, plastic quad flat pack 24 notes: 1. 80c652 and 83c652 frequency range is 1.2mhz16mhz or 1.2 to 24mhz. 2. for specification of the eprom version, see the 87c652 data sheet. 3. xxx denotes the rom code number. 4. sot311 replaced by sot307-2.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 5 temperature range ( c) freq eprom 2 drawing number and package mhz 1,2 s87c652-4n40 sot129-1 0 to +70, plastic dual in-line package 16 S87C652-4F40 0590b 0 to +70, ceramic dual in-line package w/window 16 s87c652-4a44 sot187-2 0 to +70, plastic leaded chip carrier 16 s87c652-4k44 1472a 0 to +70, ceramic leaded chip carrier w/window 16 s87c652-4b44 sot307-2 0 to +70, plastic quad flat pack 16 s87c652-5n40 sot129-1 40 to +85, plastic dual in-line package 16 s87c652-5f40 0590b 40 to +85, ceramic dual in-line package w/window 16 s87c652-5a44 sot187-2 40 to +85, plastic leaded chip carrier 16 s87c652-5b44 sot307-2 40 to +85, plastic quad flat pack 16 s87c652-7n40 sot129-1 0 to +70, plastic dual in-line package 20 s87c652-7f40 0590b 0 to +70, ceramic dual in-line package w/window 20 s87c652-7a44 sot187-2 0 to +70, plastic leaded chip carrier 20 s87c652-7k44 1472a 0 to +70, ceramic leaded chip carrier w/window 20 s87c652-8n40 sot129-1 40 to +85, plastic dual in-line package 20 s87c652-8f40 0590b 40 to +85, ceramic dual in-line package w/window 20 s87c652-8a44 sot187-2 40 to +85, plastic leaded chip carrier 20
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 6 block diagram 64k byte bus expansion contrtol prog serial port full duplex uart synchronous shift programmable i/o cpu oscillator and timing program memory data memory (256 x 8 ram) two 16-bit timer/event counters i 2 c serial i/o sda scl shared with port 1 t0 t1 counters xtal2 xtal1 frequency reference internal interrupts external interrupts control parallel ports, address/data bus and i/o pins serial in serial out shared with port 3 (8k x 8 rom) int0 int1
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 7 pin descriptions pin number mnemonic dip plcc qfp type name and function v ss 20 22 6, 16, 28, 39 i ground: 0v reference. with the qfp package all v ss pins (v ss1 to v ss4 ) must be connected. v dd 40 44 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.00.7 3932 4336 3730 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory . in this application, it uses strong internal pull-ups when emitting 1s. p1.0p1.7 18 29 4044, 13 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups, except p1.6 and p1.7 which are open drain. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). alternate functions include: p1.6 7 8 2 i/o scl: i 2 c-bus serial port clock line. p1.7 8 9 3 i/o sda: i 2 c-bus serial port data line. p2.0p2.7 2128 2431 1825 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. p3.0p3.7 1017 11, 1319 5, 713 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the 80c51 family, as listed below: 10 11 5 i rxd (p3.0): serial input port 11 13 7 o txd (p3.1): serial output port 12 14 8 i int0 (p3.2): external interrupt 13 15 9 i int1 (p3.3): external interrupt 14 16 10 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 16 18 12 o wr (p3.6): external data memory write strobe 17 19 13 o rd (p3.7): external data memory read strobe rst 9 10 4 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v dd . ale 30 33 27 i/o address latch enable: output pulse for latching the low byte of the address during an access to external memory . in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency . note that one ale pulse is skipped during each access to external data memory. psen 29 32 26 o program store enable: read strobe to external program memory via port 0 and port 2. it is activated twice each machine cycle during fetches from the external program memory . when executing out of external program memory two activations of psen are skipped during each access to external data memory . psen is not activated (remains high) during no fetches from external program memory . psen can sink/source 8 lsttl inputs and can drive cmos inputs without external pullups. ea 31 35 29 i external access: if during a reset, ea is held at ttl, level high, the cpu executes out of the internal program memory rom provided the program counter is less than 8192. if during a reset, ea is held a ttl low level, the cpu executes out of external program memory. ea is not allowed to float. xtal1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator amplifier . note: to avoid alatch-upo ef fect at power-on, the voltage on any pin at any time must not be higher than v dd + 0.5v or v ss 0.5v, respectively.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 8 table 1. 8xc652/654 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: dph dpl data pointer (2 bytes) data pointer high data pointer low 83h 82h 00h 00h af ae ad ac ab aa a9 a8 ie*# interrupt enable a8h ea es1 es0 et1 ex1 et0 ex0 0x000000b bf be bd bc bb ba b9 b8 ip*# interrupt priority b8h ps1 ps0 pt1 px1 pt0 px0 xx000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1*# port 1 90h sda scl ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h a15 a14 a13 a12 a11 a10 a9 a8 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh pcon power control 87h smod gf1 gf0 pd idl 0xxx0000b 9f 9e 9d 9c 9b 9a 99 98 s0con*# serial 0 port control 98h sm0 sm1 sm2 ren tb8 rb8 ti ri 00h s0buf# serial 0 data buffer 99h xxxxxxxxb d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h s1dat# serial 1 data dah 00h sp stack pointer 81h 07h s1adr# serial 1 address dbh ???????? slave address ???????? gc 00h s1sta# serial 1 status d9h sc4 sc3 sc2 sc1 sc0 0 0 0 f8h df de dd dc db da d9 d8 s1con*# serial 1 control d8h cr2 ens1 sta sto si aa cr1 cr0 00000000b 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h th1 timer high 1 8dh 00h th0 timer high 0 8ch 00h tl1 timer low 1 8bh 00h tl0 timer low 0 8ah 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 9 rom code protection (83c652) the 8xc652 has an additional security feature. rom code protection may be selected by setting a maskprogrammable security bit (i.e., user dependent). this feature may be requested during rom code submission. when selected, the rom code is protected and cannot be read out at any time by any test mode or by any instruction in the external program memory space. the movc instructions are the only instructions that have access to program code in the internal or external program memory. the ea input is latched during reset and is adon't careo after reset (also if the security bit is not set). this implementation prevents reading internal program code by switching from external program memory to internal program memory during a movc instruction or any other instruction that uses immediate data. oscillator characteristics xtal1 and xt al2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator, as shown in the logic symbol, page 2. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. t o insure a good power-on reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-on, the voltage on v dd and rst must come up at the same time for a proper start-up. idle mode in the idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. only the contents of the on-chip ram are preserved. a hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register pcon. table 2 shows the state of the i/o ports during low current operating modes. i 2 c serial communicationesio1 the i 2 c serial port is identical to the i 2 c serial port on the 8xc552. the operation of this subsystem is described in detail in the 8xc552 section of this manual. note that in both the 8xc652/4 and the 8xc552 the i 2 c pins are alternate functions to port pins p1.6 and p1.7. because of this, p1.6 and p1.7 on these parts do not have a pull-up structure as found on the 80c51. therefore p1.6 and p1.7 have open drain outputs on the 8xc652/4. table 2. external pin status during idle and power-down mode mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data serial control register (s1con) see table 3 cr2 ens1 sta sto si aa cr1 cr0 s1con (d8h) bits cr0, cr1 and cr2 determine the serial clock frequency that is generated in the master mode of operation. table 3. serial clock rates bit frequency (khz) at f osc cr2 cr1 cr0 6mhz 12mhz 16mhz 24mhz f osc divided by 0 0 0 23 47 62.5 94 256 0 0 1 27 54 71 107 1 224 0 1 0 31.25 62.5 83.3 125 1 192 0 1 1 37 75 100 150 1 160 1 0 0 6.25 12.5 17 25 960 1 0 1 50 100 133 1 200 1 120 1 1 0 100 200 1 267 1 400 1 60 1 1 1 0.24 < 62.5 0 to 255 0.49 < 62.5 0 to 254 0.65 < 55.6 0 to 253 0.98 < 50.0 0 to 251 96 (256 (reload value timer 1)) reload value range timer 1 (in mode 2) notes: 1. these frequencies exceed the upper limit of 100khz of the i 2 c-bus specification and cannot be used in an i 2 c-bus application.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 10 absolute maximum ratings 1, 2, 3 parameter rating unit storage temperature range 65 to +150 c voltage on any other pin to v ss 0.5 to + 6.5 v input, output current on any single pin 5 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteristics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging ef fects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. device specifications type supply voltage (v) frequency (mhz) temperature range ( c) type min. max. min. max. range ( c) p8xc652fbx 4.0 6.0 1.2 16 0 to +70 p8xc652ffx 4.0 6.0 1.2 16 40 to +85 p8xc652fhx 4.5 5.5 1.2 16 40 to +125 p8xc652ibx 4.5 5.5 1.2 24 0 to +70 p83x652ifx 4.5 5.5 1.2 24 40 to +85
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 11 dc electrical characteristics v ss = 0v test limits symbol parameter part type conditions min. max. unit v il input low voltage, except ea , p1.6/scl, p1.7/sda 0 to +70 c 0.5 0.2v dd 0.1 v 40 to +85 c 0.5 0.2v dd 0.15 v 40 to +125 c 0.5 0.2v dd 0.25 v v il1 input low voltage to ea 0 to +70 c 0.5 0.2v dd 0.3 v 40 to +85 c 0.5 0.2v dd 0.35 v 40 to +125 c 0.5 0.2v dd 0.45 v v il2 input low voltage to p1.6/scl, p1.7/sda 6 0.5 0.3v dd v v ih input high voltage, except xtal1, rst, p1.6/scl, p1.7/sda 0 to +70 c 0.2v dd +0.9 v dd +0.5 v 40 to +85 c 0.2v dd +1.0 v dd +0.5 v 40 to +125 c 0.2v dd +1.0 v dd +0.5 v v ih1 input high voltage, xtal1, rst 0 to +70 c 0.7v dd v dd +0.5 v 40 to +85 c 0.7v dd +0.1 v dd +0.5 v 40 to +125 c 0.7v dd +0.1 v dd +0.5 v v ih2 input high voltage, p1.6/scl, p1.7/sda 6 0.7v dd 6.0 v v ol output low voltage, ports 1, 2, 3, except p1.6/scl, p1.7/sda i ol = 1.6ma 8, 9 0.45 v v ol1 output low voltage, port 0, ale, psen i ol = 3.2ma 8, 9 0.45 v v ol2 output low voltage, p1.6/scl, p1.7/sda i ol = 3.0ma 0.4 v v oh output high voltage, ports 1, 2, 3, ale, psen 10 i oh = 60 m a 2.4 v i oh = 25 m a 0.75v dd v i oh = 10 m a 0.9v dd v v oh1 output high voltage; port 0 in external bus mode i oh = 800 m a 2.4 v i oh = 300 m a 0.75v dd v i oh = 80 m a 0.9v dd v i il logical 0 input current, ports 1, 2, 3, except p1.6/scl, p1.7/sda 0 to +70 c v in = 0.45v 50 m a 40 to +85 c 75 m a 40 to +125 c 75 m a i tl logical 1-to-0 transition current, ports 1, 2, 3, except p1.6/scl, p1.7/sda 0 to +70 c see note 7 650 m a 40 to +85 c 750 m a 40 to +125 c 750 m a i l1 input leakage current, port 0, ea 0.45v < v i < v dd 10 m a i l2 input leakage current, p1.6/scl, p1.7/sda 0v < v i < 6.0v 0v < v dd < 6.0v 10 m a m a i dd power supply current: see note 1 active mode @ 16mhz 2, 11 v dd =6.0v 26.5 ma active mode @ 24mhz 2, 11 v dd =5.5v 33.8 ma idle mode @ 16mhz 3, 11 6 ma idle mode @ 24mhz 3, 11 7 ma power down mode 4, 5 50 m a power down mode 4, 5 40 to +125 c 100 m a r rst internal reset pull-down resistor 50 150 k w c io pin capacitance freq.=1mhz 10 pf notes on next page.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 12 notes for dc electrical characteristics: 1. see figures 9 through 11 for i dd test conditions. 2. the operating supply current is measured with all output pins disconnected; xt al1 driven with t r = t f = 5ns; v il = v ss + 0.5v; v ih = v dd 0.5v; xtal2 not connected; ea = rst = port 0 = p1.6 = p1.7 = v dd . see figure 9. 3. the idle mode supply current is measured with all output pins disconnected; xt al1 driven with t r = t f = 5ns; v il = v ss + 0.5v; v ih = v dd 0.5v; xt al2 not connected; port 0 = p1.6 = p1.7 = v dd ; ea = rst = v ss . see figure 10. 4. the power-down current is measured with all output pins disconnected; xt al2 not connected; port 0 = p1.6 = p1.7 = v dd ; ea = rst = v ss . see figure 11. 5. 2v v pd v dd max. 6. the input threshold voltage of p1.6 and p1.7 (sio1) meets the i 2 c specification, so an input voltage below 0.3v dd will be recognized as a logic 0 while an input voltage above 0.7v dd will be recognized as a logic 1. 7. pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2v. 8. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v . in such cases, it may be desirable to qualify ale with a schmitt trigger , or use an address latch with a schmitt t rigger strobe input. 9. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol = 10ma per port pin; maximum i ol = 26ma total for port 0; maximum i ol = 15ma total for ports 1, 2, and 3; maximum i ol = 71ma total for all output pins. if i ol exceeds the test conditions, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 10. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v dd specification when the address bits are stabilizing. 11. i ddmax for other frequencies can be derived from figure 1, where freq is the external oscillator frequency in mhz. i ddmax is given in ma. 40 30 20 10 0 0 4 8 12 16 (1) maximum operating mode: v dd = v ddmax (2) maximum idle mode: v dd = v ddmax f xtal1 (mhz) i dd (ma) figure 1. i dd vs. frequency 40 30 20 10 0 0 4 8 12 16 (2) (1) 24 50 i dd (ma) f xtal1 (mhz) these values are valid within the specified frequency range. (1) maximum operating mode: v dd = v ddmax (2) maximum idle mode: v dd = v ddmax these values are valid within the specified frequency range. (1) (2)
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 13 ac electrical characteristics 1, 2 (16 mhz type) 16mhz clock variable clock symbol figure parameter min max min max unit 1/t clcl 2 oscillator frequency 1.2 16 mhz t lhll 2 ale pulse width 85 2t clcl 40 ns t avll 2 address valid to ale low 8 t clcl 55 ns t llax 2 address hold after ale low 28 t clcl 35 ns t lliv 2 ale low to valid instruction in 150 4t clcl 100 ns t llpl 2 ale low to psen low 23 t clcl 40 ns t plph 2 psen pulse width 143 3t clcl 45 ns t pliv 2 psen low to valid instruction in 83 3t clcl 105 ns t pxix 2 input instruction hold after psen 0 0 ns t pxiz 2 input instruction float after psen 38 t clcl 25 ns t aviv 2 address to valid instruction in 208 5t clcl 105 ns t plaz 2 psen low to address float 10 10 ns data memory t rlrh 3, 4 rd pulse width 275 6t clcl 100 ns t wlwh 3, 4 wr pulse width 275 6t clcl 100 ns t rldv 3, 4 rd low to valid data in 148 5t clcl 165 ns t rhdx 3, 4 data hold after rd 0 0 ns t rhdz 3, 4 data float after rd 55 2t clcl 70 ns t lldv 3, 4 ale low to valid data in 350 8t clcl 150 ns t avdv 3, 4 address to valid data in 398 9t clcl 165 ns t llwl 3, 4 ale low to rd or wr low 138 238 3t clcl 50 3t clcl +50 ns t avwl 3, 4 address valid to wr low or rd low 120 4t clcl 130 ns t qvwx 3, 4 data valid to wr transition 3 t clcl 60 ns t dw 3, 4 data setup time before wr 288 7t clcl 150 ns t whqx 3, 4 data hold after wr 13 t clcl 50 ns t rlaz 3, 4 rd low to address float 0 0 ns t whlh 3, 4 rd or wr high to ale high 23 103 t clcl 40 t clcl +40 ns shift register t xlxl 5 serial port clock cycle time 3 0.75 12t clcl m s t qvxh 5 output data setup to clock rising edge 3 492 10t clcl 133 ns t xhqx 5 output data hold after clock rising edge 3 80 2t clcl 117 ns t xhdx 5 input data hold after clock rising edge 3 0 0 ns t xhdv 5 clock rising edge to input data valid 3 492 10t clcl 133 ns external clock t chcx 6 high time 3 20 20 t clcl t clcx ns t clcx 6 low time 3 20 20 t clcl t chcx ns t clch 6 rise time 3 20 20 ns t chcl 6 fall time 3 20 20 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf , load capacitance for all other outputs = 80pf . 3. these values are characterized but not 100% production tested.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 14 ac electrical characteristics 1, 2 (24 mhz type) 24mhz clock variable clock symbol figure parameter min max min max unit 1/t clcl 2 oscillator frequency 1.2 24 mhz t lhll 2 ale pulse width 43 2t clcl 40 ns t avll 2 address valid to ale low 17 t clcl 25 ns t llax 2 address hold after ale low 17 t clcl 25 ns t lliv 2 ale low to valid instruction in 102 4t clcl 65 ns t llpl 2 ale low to psen low 17 t clcl 25 ns t plph 2 psen pulse width 80 3t clcl 45 ns t pliv 2 psen low to valid instruction in 65 3t clcl 60 ns t pxix 2 input instruction hold after psen 0 0 ns t pxiz 2 input instruction float after psen 17 t clcl 25 ns t aviv 2 address to valid instruction in 128 5t clcl 80 ns t plaz 2 psen low to address float 10 10 ns data memory t rlrh 3, 4 rd pulse width 150 6t clcl 100 ns t wlwh 3, 4 wr pulse width 150 6t clcl 100 ns t rldv 3, 4 rd low to valid data in 118 5t clcl 90 ns t rhdx 3, 4 data hold after rd 0 0 ns t rhdz 3, 4 data float after rd 55 2t clcl 28 ns t lldv 3, 4 ale low to valid data in 180 8t clcl 150 ns t avdv 3, 4 address to valid data in 210 9t clcl 165 ns t llwl 3, 4 ale low to rd or wr low 75 175 3t clcl 50 3t clcl +50 ns t avwl 3, 4 address valid to wr low or rd low 92 4t clcl 75 ns t qvwx 3, 4 data valid to wr transition 12 t clcl 30 ns t dw 3, 4 data setup time before wr 162 7t clcl 130 ns t whqx 3, 4 data hold after wr 17 t clcl 25 ns t rlaz 3, 4 rd low to address float 0 0 ns t whlh 3, 4 rd or wr high to ale high 17 67 t clcl 25 t clcl +25 ns shift register t xlxl 5 serial port clock cycle time 3 0.5 12t clcl m s t qvxh 5 output data setup to clock rising edge 3 283 10t clcl 133 ns t xhqx 5 output data hold after clock rising edge 3 23 2t clcl 60 ns t xhdx 5 input data hold after clock rising edge 3 0 0 ns t xhdv 5 clock rising edge to input data valid 3 283 10t clcl 133 ns external clock t chcx 6 high time 3 17 17 t clcl t clcx ns t clcx 6 low time 3 17 17 t clcl t chcx ns t clch 6 rise time 3 5 5 ns t chcl 6 fall time 3 5 5 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf , load capacitance for all other outputs = 80pf . 3. these values are characterized but not 100% production tested.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 15 ac electrical characteristics i 2 c interface symbol parameter input output scl timing characteristics t hd;sta start condition hold time 14 t clcl > 4.0 m s 1 t low scl low time 16 t clcl > 4.7 m s 1 t high scl high time 14 t clcl > 4.0 m s 1 t rc scl rise time 1 m s 2 t fc scl fall time 0.3 m s < 0.3 m s 3 sda timing characteristics t su;dat1 data set-up time 250ns > 20 t clcl t rd t su;dat2 sda set-up time (before rep. start cond.) 250ns > 1 m s 1 t su;dat3 sda set-up time (before stop cond.) 250ns > 8 t clcl t hd;dat data hold time 0ns > 8 t clcl t fc t su;sta repeated start set-up time 14 t clcl > 4.7 m s 1 t su;sto stop condition set-up time 14 t clcl > 4.0 m s 1 t buf bus free time 14 t clcl > 4.7 m s 1 t rd sda rise time 1 m s 2 t fd sda fall time 0.3 m s < 0.3 m s 3 notes: 1. at 100 kbit/s. at other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. determined by the external bus-line capacitance and the external bus-line pull-resistor , this must be < 1 m s. 3. spikes on the sda and scl lines with a duration of less than 3 t clcl will be filtered out. maximum capacitance on bus-lines sda and scl = 400pf. 4. t clcl = 1/f osc = one oscillator clock period at pin xt al1. for 63ns (42ns) < t clcl < 285ns (16mhz (24mhz) > f osc > 3.5mhz) the si01 interface meets the i 2 c-bus specification for bit-rates up to 100 kbit/s. timing sio1 (i 2 c) interface t rd t su;sta t buf t su; sto 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd t fd t rc t fc t high t low t hd;sta t su;dat1 t hd;dat t su;dat2 t su;dat3 start condition repeated start condition sda (input/output) scl (input/output) stop condition start or repeated start condition
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 16 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t pxiz figure 2. external program memory read cycle ale psen port 0 port 2 a8a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t pliv t lhll t plph t lliv t plaz t llpl t aviv ale psen port 0 port 2 figure 3. external data memory read cycle rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a8a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 17 t llax ale psen port 0 port 2 figure 4. external data memory write cycle wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dph a8a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t dw 0 1 2 3 4 5 6 7 8 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv figure 5. shift register mode timing
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 18 v ih1 0.8v t chcl t clcl t clch t clcx t chcx figure 6. external clock drive at xtal1 v dd 0.5 0.45v 0.2v dd +0.9 0.2v dd 0.1 note: ac inputs during testing are driven at v dd 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. figure 7. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol > + 20ma. figure 8. float waveform timing reference points
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 19 v dd p0 ea rst xtal1 xtal2 v ss v dd v dd v dd i dd (nc) clock signal figure 9. i dd test condition, active mode all other pins are disconnected v dd p0 rst xtal1 xtal2 v ss v dd v dd i dd (nc) clock signal p1.6 p1.7 p1.6 p1.7 ea * * * * figure 10. i dd test condition, idle mode all other pins are disconnected v dd p0 rst xtal1 xtal2 v ss v dd v dd i dd (nc) figure 11. i dd test condition, power down mode all other pins are disconnected. v dd = 2v to 5.5v p1.6 p1.7 ea * * note: * ports 1.6 and 1.7 should be connected to v cc through resistors of suf ficiently high value such that the sink current into these pins does not exceed the i ol1 specification. purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011.
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 20 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 21 plcc44: plastic leaded chip carrier; 44 leads sot187-2
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 22 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 23 0590b 40-pin (600 mils wide) ceramic dual in-line (f) package (with window (fa) package) notes: 1. controlling dimension: inches. millimeters are 2. dimension and tolerancing per ansi y14. 5m-1982. 3. ato, ado, and aeo are reference datums on the body 4. these dimensions measured with the leads 5. pin numbers start with pin #1 and continue 6. denotes window location for eprom products. and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. constrained to be perpendicular to plane t. counterclockwise to pin #40 when viewed shown in parentheses. from the top. d pin # 1 e 0.225 (5.72) max. 0.010 (0.254) t e d 0.023 (0.58) 0.015 (0.38) 0.165 (4.19) 0.125 (3.18) 0.070 (1.78) 0.050 (1.27) t seating plane 0.620 (15.75) 0.590 (14.99) (note 4) 0.598 (15.19) 0.571 (14.50) bsc 0.600 (15.24) 0.695 (17.65) 0.600 (15.24) (note 4) 0.015 (0.38) 0.010 (0.25) 0.175 (4.45) 0.145 (3.68) 0.055 (1.40) 0.020 (0.51) 0.100 (2.54) bsc 2.087 (53.01) 2.038 (51.77) 0.098 (2.49) 0.040 (1.02) 0.098 (2.49) 0.040 (1.02) see note 6 8530590b 06688
phlips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers 1996 aug 15 24 1472a 44-pin cerquad j-bend (k) package notes: 1. all dimensions and tolerances to conform 2. uv window is optional. 3. dimensions do not include glass protrusion. glass protrusion to be 0.005 inches maximum 4. controlling dimension millimeters. 5. all dimensions and tolerances include lead trim of fset and lead plating finish. 6. backside solder relief is optional and dimensions are for reference only . 1.02 (0.040) x 45 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) chamfer 45 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) on each side. to ansi y14.51982. 2 3 3 x 0.63 (0.025) r min. 3.05 (0.120) 2.29 (0.090) 4.83 (0.190) 3.94 (0.155) seating plane 0.38 (0.015) 0.51 (0.02) x 45 6 6 17.65 (0.656) 17.40 (0.685) 1.27 (0.050) 12.7 (0.500) 8.13 (0.320) 7.37 (0.290) 40x 4.83 (0.190) 3.94 (0.155) seating plane 0.15 (0.006) min. 0.25 (0.010) r min. 0.508 (0.020) r min. 0.25 (0.010) 0.15 (0.006) 90 + 5 10 0.076 (0.003) min. detail b mm/(inch) see det ail b see det ail a detail a typ. all sides mm/(inch) 1.52 (0.060) ref . 0.482 (0.019 + 0.002) seating plane 1.02 + 0.25 (0.040 + 0.010) base plane 45 typ. 4 places 0.73 + 0.08 (0.029 + 0.003) 1.27 (0.050) typ. nominal 8.13 (0.320) 7.37 (0.290) 3 853-1472a 05854
philips semiconductors product specification 80c652/83c652 cmos single-chip 8-bit microcontrollers
philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appliances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonably be expected to result in a personal injury . philips semiconductors and philips electronics north america corporation customers using or selling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1996 all rights reserved. printed in u.s.a.

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